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d a t a sh eet product speci?cation file under integrated circuits, ic01 1998 feb 16 integrated circuits SZA1000 qic digital equalizer
1998 feb 16 2 philips semiconductors product speci?cation qic digital equalizer SZA1000 features 3-wire serial interface for programming and status reading suitable for mfm (modified frequency modulation), rll 1,7 (run length limited) and similar codes transfer rates with mfm code from 250 kbits/s to 4 mbits/s transfer rates with rll(1,7) code from 500 kbits/s to 12 mbits/s programmable fir (finite impulse-response) filter makes it possible to equalize complex and asymmetric channel impulse responses programmable fixed and tracking qualification thresholds provide reliable data recovery in read mode, and reliable bad sector detection in verify mode read pulse output for floppy tape drives digital data synchronizer based on digital pll with maximum likelihood detector for a better error rate than can be achieved with conventional analog circuits data verification can be used (with the maximum likelihood detector switched off) to find bad sectors on drives with conventional read electronics servo stripe detection for tr4, qic3080 and similar formats gap detector 2 programmable current sources peak-to-peak amplitude detector with lowpass filter for servo burst reading fully digital pll for clock and data recovery: C fully programmable behaviour C no external components, no tolerance problems C programmable window shift C fast run-in capability C ideal zero phase restart. parallel 8-bit input and output for product development and production testing programmable weq (write equalization) circuit with transfer rates of up to 2 mbits/s for floppy tape drives and up to 8 mbits/s for drives with internal controllers. general description the SZA1000 is a single chip digital equalizer for single channel qic (quarter inch cartridge) systems with mr (magneto resistive) heads. it can be used with qic 3010, qic 3020, qic 3080, qic 3095, travan 2, 3, 4 and 5, and similar formats. it replaces a pulse detector, programmable filter and data synchronizer, and adds a fir filter to the conventional analog solution. this makes it possible to equalize yoke-type mr heads as well as sig (sensor in gap) mr heads. quick reference data ordering information symbol parameter conditions min. typ. max. unit v ddd1 ; v ddd2 digital supply voltage 4.5 5.0 5.5 v v dda1 ; v dda2 analog supply voltage 4.5 5.0 5.5 v i ddd1 ; i ddd2 digital supply current f s =24mhz - 32 - ma i dda1 ; i dda2 analog supply current - 50 - ma f clk(clkin) read circuit clock frequency - 24 24 mhz f clk(weqclk) weq circuit clock frequency - 24 36 mhz t amb ambient operating temperature 0 - 70 c type number package name description version SZA1000h qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm) body 10 10 1.75 mm sot307-2
1998 feb 16 3 philips semiconductors product speci?cation qic digital equalizer SZA1000 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... block diagram a ndbook, full pagewidth mgg582 xosc/ clk in i/o mux mux write equalization serial interface idac lpf 15 khz diff pll ampl. detector dac maximum likelihood detector lpf 8 mhz ampl. qualifier + gap detector stripe detector read pulse adc hpf fir clk div lpf r interpol r 22 38 1 2 43 40 cmpb eyea cmpa eyeb 39 44 24 23 36 4 3 9 10 33 32 31 30 37 8, 28, 34, 41 5, 26, 35, 42 v ssd1 v ddd1 v ssd2 v ddd2 v ssa1 v dda1 v ssa2 v dda2 11 to 18 8 27 25 21 srd/rd 19 ltd 20 rg 6 clkin 7 clkout rrc gap/stripe sdio sclk sden weqen weqclk wdin auxbus0/wdout test inb ina v ref reset wgate wgx auxbus1 to auxbus7 29 paclk SZA1000 io2 io1 r ref 44 fig.1 block diagram.
1998 feb 16 4 philips semiconductors product speci?cation qic digital equalizer SZA1000 pinning symbol pin description io1 1 programmable current source io2 2 programmable current source weqen 3 write equalization circuit enable input wga te 4 write gate input; active low v ddd1 5 digital supply voltage clkin 6 external clock or crystal oscillator input clkout 7 crystal oscillator output v ssd1 8 digital ground weqclk 9 write equalization circuit clock input wdin 10 write equalization circuit data input auxbus0/wdout 11 bit 0 auxiliary i/o bus or write equalization output to write amplifier auxbus1 12 bit 1 auxiliary i/o bus auxbus2 13 bit 2 auxiliary i/o bus auxbus3 14 bit 3 auxiliary i/o bus auxbus4 15 bit 4 auxiliary i/o bus auxbus5 16 bit 5 auxiliary i/o bus auxbus6 17 bit 6 auxiliary i/o bus auxbus7 18 bit 7 auxiliary i/o bus l td 19 fast lock to data input; active low rg 20 read gate input gap/stripe 21 gap or stripe detector output sdio 22 serial interface data input and output sden 23 serial interface enable input sclk 24 serial interface clock input rrc 25 read reference clock output v ddd2 26 digital supply voltage srd/rd 27 synchronized read data or read data output v ssd2 28 digital ground paclk 29 pre-amp clock output reset 30 reset input; active low test 31 test input; connect to ground ina 32 analog signal from read amplifier; positive input inb 33 analog signal from read amplifier; negative input v ssa1 34 analog ground v dda1 35 analog supply voltage wgx 36 extended write gate output for floppy tape drives; active low v ref 37 positive a/d reference voltage input r ref 38 connect external resistor eyea 39 differentiated signal; positive output cmpa 40 comparator for read pulse; positive input
1998 feb 16 5 philips semiconductors product speci?cation qic digital equalizer SZA1000 v ssa2 41 analog ground v dda2 42 analog supply voltage cmpb 43 comparator for read pulse; negative input eyeb 44 differentiated signal; negative output symbol pin description fig.2 pin configuration. handbook, full pagewidth SZA1000 mgd794 1 2 3 4 5 6 7 8 9 10 11 io1 io2 weqen wgate v ddd1 clkin clkout v ssd1 weqclk wdin auxbus0/wdout inb ina test reset paclk v ssd2 srd/rd v ddd2 rrc sclk sden 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 auxbus1 auxbus2 auxbus3 auxbus4 auxbus5 auxbus6 auxbus7 ltd rg gap/stripe sdio eyeb cmpb v dda2 v ssa2 cmpa eyea r ref v ref wgx v dda1 v ssa1 44 43 42 41 40 39 38 37 36 35 34
1998 feb 16 6 philips semiconductors product speci?cation qic digital equalizer SZA1000 functional description clock oscillator and divider the clock source for the SZA1000 can be a crystal connected between pins 6 and 7, or an external clock signal connected to pin 6. this clock frequency is divided by a number programmable between 1 and 8 (see tables 27 and 28). the resulting frequency, f s , is used as clock input to all on-chip circuits except the write equalizer. the frequency of the paclk output signal (pin 29) is equal to f s . adc the 8-bit adc has a differential input. the total adc conversion range is 1.6 v (p-p; differential). the adc sample rate is equal to f s . high-pass ?lter after the adc this is a first order filter with a cut-off frequency of it removes the dc component of the signal. low-pass ?lter this low-pass filter is an even symmetrical fir (finite impulse response) filter. the number of taps depends on the sample rate reduction factor r (see tables 30 and 31). the filter has 8 taps for r = 1 or 14 taps for r = 2 (see table 7). the middle taps have a fixed coefficient value of +128, the coefficients of the other taps are programmable in the range - 128 to +127 (see table 6). fir this transversal filter has 6 taps with the sample rate equal to f s (r = 1), or 11 taps with the sample rate equal to 1 2 f s (r = 2). tap 10 has a fixed coefficient value of +64, the coefficients of the other taps are programmable between - 64 and +63 (see table 2). the filter has 19 signal delay sections. the position of each tap can be selected from a subset of the 20 possible positions (see tables 3 and 4). interpolator if a sample rate of 1 2 f s has been selected for the fir (r = 2), it is increased once again to f s at the interpolator. f s 1608 ------------ - amplitude detector this circuit has a separate rectifier and a positive and negative peak detector. typical rise time (0 to 70%) for a normal mfm or rll 1,7 code input signal is , typical decay time (100 to 30%) is programmable between and (see tables 10 and 11). the output is an 8-bit number that can be polled via the serial interface. in addition, the peak-to-peak value is calculated and filtered by a first order low-pass filter with a cut-off frequency of both the filtered and unfiltered amplitudes can be read via the serial interface (see table 44) or via the parallel output bus. amplitude quali?er a peak is considered valid if its amplitude is above a qualification threshold. separate qualification thresholds are used for the positive and negative peaks. each threshold is the greater of: a programmable level (qual_fix_ pos and qual_fix_neg; control register addresses 24 and 25) a programmable fraction ( 1 2 , 3 8 , 1 4 , 1 8 or 0; see tables 9 and 12) of the peak amplitude of the incoming signal. gap detector when the peak-to-peak amplitude of the measured signal is below a preset limit (gap_thresh; control register address 28), the gap detector output is high, otherwise low (gap output on pin 21 must be selected; see table 22). 1 f s --- - 500 f s --------- - 400 f s --------- - f s 3217 ------------ -
1998 feb 16 7 philips semiconductors product speci?cation qic digital equalizer SZA1000 stripe detector this circuit is used to signal the stripes in qic 3080, qic 3095 and tr4 servo formats (stripe output on pin 21 must be selected; see table 22). a frequency detector counts the peaks above the qualification threshold (see table 29). an input signal containing frequencies within 25% of the programmable nominal frequency will be detected as a stripe. the microcontroller can then poll the amplitude of the following burst via the serial interface. differentiator this function is realized by subtracting samples. the delay between samples is programmable between 1 and 6 periods of f s , split into two parts to provide a balanced delay between the differentiated and non-differentiated signals (see tables 24 to 26). the pll this is a fully digital pll (phase lock loop) with a programmable nominal frequency (see tables 35 and 36), zero phase restart, programmable window shift (win_shift; control register address 42) and a loop filter with two separate programmable settings. the pll output reference clock is the rrc signal (pin 25; see table 34). the frequency of this signal is rounded in time to f s . the pll is switched to the nominal frequency if rg (pin 20) is low, and makes a zero phase restart at the first detected peak after rg goes high. the ltd input (pin 19) is used to select between the two loop filter settings (see tables 37 to 42). this allows for fast lock-in during preamble, before switching to a lower loop bandwidth for maximum data reliability (see fig.3). fig.3 pll timing diagram. handbook, halfpage mgg583 input signals rg pll mode preamble data nominal frequency fast lock-in normal read mode zero phase restart ltd the maximum likelihood detector this detector calculates the most likely position of the peaks in the signal. it checks for (d,k) code constraints, and for alternating peaks. if an error is detected, the most likely correction is implemented. separate corrections can be enabled or disabled. the srd output of the maximum likelihood detector is valid during the rising edge of the rrc signal (see fig.4). the maximum likelihood detector is used only to generate the srd signal, and not to generate the time continuous rd pulse. the dac this is an internal differential 8-bit dac operating at f s . the lpf after the dac this analog lpf filters the time quantized signal from the dac to retain a time continuous signal. this provides more accurate timing of the detected zero crossings in the rd pulse output. the lpf is a second order active filter with a cut-off frequency of 8 mhz. the read pulse circuit a peak in the equalized signal at the interpolator output generates a read pulse. the peak is detected if a zero crossing occurs in the filtered signal after the dac while the non-differentiated signal is above the qualification threshold. uncommitted current sources two uncommitted 5-bit programmable current sink dacs (0 to 2 ma) are available as io1 and io2 (see table 20 for programming). these could be used, for example, to drive the tape hole detector circuit. fig.4 srd/rrc timing. handbook, halfpage mgg584 srd rrc
1998 feb 16 8 philips semiconductors product speci?cation qic digital equalizer SZA1000 parallel state bus all internal digital signals can be monitored via an 8-bit parallel bus. an external dac or an evaluation tool such as a phase error logger for tia (time interval analyzer), drop-out and symmetry measurements can be connected to this bus for evaluation purposes (see table 34). write equalization this circuit has an independent clock input weqclk at pin 9. write equalization can be programmed to conform to a number of formats including qic 3010, qic 3020, qic 3080, qic 3095, qic 5010, travan 2, travan 3 and travan 4. this is achieved by programming the circuit to divide a channel bit-cell into 2, 3 or 6 time slots (see tables 13 and 14). the external weq clock frequency should be selected such that an integer number of between 1 and 8 clock periods fits in a time slot (see tables 18 and 19). the width and position of the inserted write pulse can be programmed (see tables 15 to 17). the write equalization circuit input and output signals can be independently programmed to be in either wd or wdi format (see table 15). for qic 3010 or 3020, the recording signal is typically generated by a circuit that uses a separate crystal. an input buffer with variable delay is used to prevent errors occurring in the recorded signal. this buffer is set to its nominal position when writing begins. signals longer than a data block can be recorded during formatting. to avoid overloading the time buffer, the circuit can resynchronize automatically during gaps in the qic 3010 or 3020 format. serial interface the serial interface uses 8-bit addresses and 8-bit data. its timing is shown in fig.5. ic mode settings, filter coefficients, scale factors and thresholds can be loaded via the serial interface. measured signal amplitude, for example burst level measurement at qic 3095 or agc control by the microcontroller, and the actual pll frequency can be read via the serial interface. to read data from the status registers, hex address ff must be transmitted along with the required data code. the ic will then respond with the contents of the appropriate 8-bit status register (see table 44).
1998 feb 16 9 philips semiconductors product speci?cation qic digital equalizer SZA1000 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... fig.5 serial i/o timing diagrams. k , full pagewidth mgg585 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 3-state write settings sden sclk sdio a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 3-state read status sden sclk sdio address and data from microcontroller data out from device
1998 feb 16 10 philips semiconductors product speci?cation qic digital equalizer SZA1000 control register control register settings the control register is accessible through the serial interface and contains 46 8-bit entries as shown in table 1. table 1 control register address name description 0 fir_val0 fir tap 0 coefficient value (see table 2) 1 fir_val1 fir tap 1 coefficient value 2 fir_val2 fir tap 2 coefficient value 3 fir_val3 fir tap 3 coefficient value 4 fir_val4 fir tap 4 coefficient value 5 fir_val5 fir tap 5 coefficient value 6 fir_val6 fir tap 6 coefficient value 7 fir_val7 fir tap 7 coefficient value 8 fir_val8 fir tap 8 coefficient value 9 fir_val9 fir tap 9 coefficient value 10 fir_sel05 fir tap positions (see tables 3 and 4) 11 fir_sel16 fir tap positions 12 fir_sel27 fir tap positions 13 fir_sel38 fir tap positions 14 fir_sel49 fir tap positions 15 fir_sel10 fir tap positions 16 fir_shift fir output scaling (see table 5) 17 lpf_val1 lpf tap coefficient value (see table 6) 18 lpf_val4 lpf tap coefficient value 19 lpf_val2 lpf tap coefficient value 20 lpf_val5 lpf tap coefficient value 21 lpf_val3 lpf tap coefficient value 22 lpf_val6 lpf tap coefficient value 23 lpf_shift lpf output scaling (see table 8) 24 qual_fix_pos amplitude qualifier positive fixed qualification threshold 25 qual_fix_neg amplitude qualifier negative fixed qualification threshold 26 qual_var_gain amplitude qualifier variable gain factors (see tables 9 and 12) 27 qual_slope_del amplitude detector slope qualification delay (see table 10) 28 gap_thresh gap detector fixed threshold 29 weq_set0 weq settings (see tables 13 and 14) 30 weq_set1 weq settings (see tables 15, 16 and 17) 31 weq_clk_div weq clock divider (see tables 18 and 19) 32 - not used 33 idac1 io1 dac current (see table 20) 34 idac2 io2 dac current (see table 20)
1998 feb 16 11 philips semiconductors product speci?cation qic digital equalizer SZA1000 control register functions control register functions are detailed in tables 2 to 43. fir function addresses 0 to 9: fir tap coef?cient values table 2 coef?cient values: fir_val0 to fir_val9; note 1 note 1. these are 7-bit coefficient values in twos complement notation; taps 5 to 9 are only used when r = 2; tap 10 has a fixed coefficient value of +64. addresses 10 to 15: fir tap position selection table 3 tap position selection: fir_selnn; note 1 note 1. see table 4 for the value of fsn.n. 35 eq mode0 mode setting for paclk (pin 29) and gap/stripe (pin 21) (see tables 21, 22 and 23) 36 diff differentiator settings (see tables 24, 25 and 26) 37 clk_div main clock divider (see tables 27 and 28) 38 stripe_f stripe detector nominal frequency (see table 29) 39 eq_mode1 equalizer mode settings 40 pll_freql pll nominal frequency bits 0 to 7 41 pll_freqh pll nominal frequency bits 8 to 10 42 win_shift pll window shift 43 pll_ni pll loop filter integrating gain and range 44 pll_np pll loop filter proportional gain 45 mld_set maximum likelihood detector settings d7 d6 d5 d4 d3 d2 d1 d0 - fir_valn.6 fir_valn.5 fir_valn.4 fir_valn.3 fir_valn.2 fir_valn.1 fir_valn.0 addr. name taps d7 d6 d5 d4 d3 d2 d1 d0 10 fir_sel05 0 and 5 -- fs0.2 fs0.1 fs0.0 fs5.2 fs5.1 fs5.0 11 fir_sel16 1 and 6 -- fs1.2 fs1.1 fs1.0 fs6.2 fs6.1 fs6.0 12 fir_sel27 2 and 7 -- fs2.2 fs2.1 fs2.0 fs7.2 fs7.1 fs7.0 13 fir_sel38 3 and 8 -- fs3.2 fs3.1 fs3.0 fs8.2 fs8.1 fs8.0 14 fir_sel49 4 and 9 -- fs4.2 fs4.1 fs4.0 fs9.2 fs9.1 fs9.0 15 fir_sel10 10 ---- fs10.3 fs10.2 fs10.1 fs10.0 address name description
1998 feb 16 12 philips semiconductors product speci?cation qic digital equalizer SZA1000 table 4 translation table: fs selection bits (fsn.n from table 3) to tap position address 16: fir output scaling table 5 output scaling: fir_shift l ow - pass filter functions addresses 17 to 22: lpf tap coef?cient values table 6 coef?cient value: lpf_val1 to lpf_val6; notes 1 and 2 notes 1. these are 8-bit coefficient values in twos complement notation; taps 4 to 6 are only used when r = 2. 2. see table 7 for the values of lpf_valn.n fsn tap 0,5 tap 1,6 tap 2,7 tap 3,8 tap 4,9 tap 10 01296302 113107413 214118524 315129635 4 161310 7 4 6 5171411857 6 181512 9 6 8 7 19161310 7 9 8 ----- 10 9 ----- 11 10 ----- 12 11 ----- 13 12 ----- 14 13 ----- 15 14 ----- 16 15 ----- 17 fir_shift (binary) fir output scaling gain factor 00000001 1 00000010 2 00000100 4 00001000 8 00010000 16 00100000 32 01000000 64 10000000 128 d7 d6 d5 d4 d3 d2 d1 d0 lpf_valn.7 lpf_valn.6 lpf_valn.5 lpf_valn.4 lpf_valn.3 lpf_valn.2 lpf_valn.1 lpf_valn.0
1998 feb 16 13 philips semiconductors product speci?cation qic digital equalizer SZA1000 table 7 lpf tap positions address 23: lpf output scaling table 8 output scaling: lpf_shift a mplitude qualifier / detector functions address 24: qual_fix_pos and address 25: qual_fix_neg qual_fix_pos and qual_fix_neg contain the positive and negative fixed threshold (8-bit signed) values. address 26: variable gain factors table 9 gain factors: qual_var_gain; note 1 note 1. gp and gn set the factors of the measured amplitude that are to be used as variable qualifier thresholds: gp for the positive peaks and gn for the negative peaks. tap position coefficient values r = 1 coefficient values r = 2 0 lpf_val3 lpf_val6 1 lpf_val2 lpf_val5 2 lpf_val1 lpf_val4 3 +128 lpf_val3 4 +128 lpf_val2 5 lpf_val1 lpf_val1 6 lpf_val2 +128 7 lpf_val3 +128 8 0 lpf_val1 9 0 lpf_val2 10 0 lpf_val3 11 0 lpf_val4 12 0 lpf_val5 13 0 lpf_val6 lpf_shift (binary) lpf output scaling gain factor 00000001 1 00000010 2 00000100 4 00001000 8 00010000 16 00100000 32 01000000 64 10000000 128 d7 d6 d5 d4 d3 d2 d1 d0 -- gp.2 gp.1 gp.0 gn.2 gn.1 gn.0
1998 feb 16 14 philips semiconductors product speci?cation qic digital equalizer SZA1000 address 27: amplitude detector slope quali?cation delay table 10 quali?cation delay: qual_slope_del; notes 1 and 2 notes 1. del is the programmable compensation delay, in cycles of f s , between the qualifier and the analog zero crossing of the read pulse circuit; del is a 2-bit unsigned value 2. sl selects the decay time of the amplitude detectors. d7 d6 d5 d4 d3 d2 d1 d0 ---- del.1 del.0 sl.1 sl.0 table 11 amplitude detector decay time sl decay time 0 1 2 3 500 f s --------- - 500 f s --------- - 1000 f s ------------ - 2000 f s ------------ - 4000 f s ------------ - table 12 variable quali?er threshold gp, gn variable threshold 00 1 1 8 2 1 4 3 3 8 4, 5, 6, 7 1 2 g ap detector functions address 28: fixed threshold: gap_thresh fixed threshold for the gap detector; 8-bit signed value. w rite e qualization (weq) functions address 29: weq settings table 13 time slots: weq_set0; see table 14 table 14 time slots in channel bit cell d7 d6 d5 d4 d3 d2 d1 d0 ----- n6 n3 n2 number of time slots n6 n3 n2 2001 3010 6100
1998 feb 16 15 philips semiconductors product speci?cation qic digital equalizer SZA1000 address 30: weq settings table 15 weq_set1; notes 1 to 4, see also tables 16 and 17. notes 1. if bit wdi_o is high, the circuit output is a wd signal, else a wdi signal. 2. if bit wdi_i is high, the circuit expects a wd signal at the input, else a wdi signal. 3. if the resync bit is high, the weq circuit resynchronizes its time buffer during a gap in the qic 3010 or qic 3020 format; this setting is only permitted if 6 time slots in a bit-cell are selected (n6 = 1; see table 14). 4. tps sets the position of the inserted write equalization pulse, tws sets its width. d7 d6 d5 d4 d3 d2 d1 d0 wdi_o wdi_i resync tps2 tps1 tps0 tws1 tws0 fig.6 wd/wdi signal timing. handbook, halfpage mgg586 wd wdi fig.7 position and width of write equalization pulse. handbook, halfpage mgg587 t d t w 1 t 1.5 t 2 t, etc. to 4 t 101 10 1 100 0 01
1998 feb 16 16 philips semiconductors product speci?cation qic digital equalizer SZA1000 table 16 write equalization pulse position tps position in time slots 01 12 23 34 45 56 67 78 table 17 write equalization pulse width tws width in time slots 0 weq off 11 22 33 address 31: weq circuit clock divider table 18 division factor: weq_clk_div; note 1 note 1. wcd sets the division factor between weqclk and the frequency of the time slot. d7 d6 d5 d4 d3 d2 d1 d0 ----- wcd.2 wcd.1 wcd.0 table 19 weq clock division wcd weq clock division factor 01 12 23 34 45 56 67 78 u ncommitted current dac functions addresses 33 and 34: current dacs table 20 dac current: idac1 and idac2; note 1 note 1. these are 5-bit unsigned numbers; the dac current is ma. d7 d6 d5 d4 d3 d2 d1 d0 --- idn.4 idn.3 idn.2 idn.1 idn.0 idn 16 --------- -
1998 feb 16 17 philips semiconductors product speci?cation qic digital equalizer SZA1000 o/p signal function : pins 21 and 29 address 35: o/p select pins 21 and 29 table 21 output signal select: eq mode 0; see tables 22 and 23 d7 d6 d5 d4 d3 d2 d1 d0 ---- pa.1 pa.0 gap.1 gap.0 table 22 output signal: pin 21 notes 1. gap, stripe or qual may be selected to detect gaps, stripes or valid signal peaks. all are active high. 2. see also table 34. 3. the rd output (read pulse): falling edge active. gap output signal on pin 21 0 gap (1) 1 stripe 2 qual (2) 3rd (3) table 23 output signal: pin 29 pa output signal on pin 29 0f s - paclk on 1 1 - paclk off 2 0 - paclk off 3 0 - paclk off d ifferentiator functions address 36: differentiator settings table 24 diff; note 1 note 1. dl1 and dl2 are programmable delays for the differentiator; ds is the gain factor of the differentiated signal. d7 d6 d5 d4 d3 d2 d1 d0 --- ds dl2.1 dl2.0 dl1.1 dl1.0 table 25 differentiator delay; notes 1 and 2 notes 1. dl1 and dl2 are added to provide a maximum delay of 6 f s cycles. 2. it is advisable to have dl1 and dl2 equal to avoid adding unwanted delay in the differentiator. dln delay in f s cycles 00 11 22 33 table 26 differentiator gain factor ds output scaling gain factor 04 12
1998 feb 16 18 philips semiconductors product speci?cation qic digital equalizer SZA1000 c lock functions address 37: main clock divider table 27 clock divider: clk_div; note 1 note 1. cd selects the main clock division factor. the clkin frequency (pin 6) divided by this factor gives the ics operating frequency f s (apart from the weq circuit). d7 d6 d5 d4 d3 d2 d1 d0 ----- cd.2 cd.1 cd.0 table 28 clock division factor cd clock division 01 12 23 34 45 56 67 78 s tripe detector functions address 38: stripe detector nominal frequency table 29 quali?cation threshold: stripe_f; note 1 note 1. sf is an unsigned 5-bit value used to determine the detection threshold for the stripe detector. the nominal detection frequency is auxbus, pins 25 and 27, sample rate reduction and stand - by functions address 39: equalizer mode settings table 30 eq_mode 1; note 1, see also tables 31 to 34 note 1. r1 selects the filter sample rate reduction factor; stby1 and stby2 are the dac and adc power on/off switches; st selects output signal modes for pins 25 and 27. d7 d6 d5 d4 d3 d2 d1 d0 --- sf.4 sf.3 sf.2 sf.1 sf.0 d7 d6 d5 d4 d3 d2 d1 d0 - stby2 st.3 st.2 st.1 st.0 stby1 r1 f s 3sf1 + () --------------------------------- -
1998 feb 16 19 philips semiconductors product speci?cation qic digital equalizer SZA1000 table 31 fir/lpf sample rate reduction factor: r r1 r 02 11 table 32 dac power stby1 d/a power 0on 1off table 33 adc power stby2 a/d power 0on 1off table 34 mode settings: pins 25, 27 and auxbus notes 1. qual is a test signal (active high) used to detect valid signal peaks (see also table 22). 2. when comp is selected, pin 25 is switched to the output of the read pulse circuit comparator for test purposes. pll functions addresses 40 and 41: pll nominal frequency table 35 pll_freql (address 40) table 36 pll_freqh (address 41); note 1 note 1. the nominal pll frequency is st ic mode pin 27 pin 25 auxbus 0 pll off rd qual (1) bit 0: wdout, bits 1 to 7 high-z 1 pll off rd comp (2) bit 0: wdout, bits 1 to 7 high-z 2 pll on srd rrc bit 0: wdout, bits 1 to 7 high-z 3 adc test srd rrc adc output 4 dac test rd comp dac output 5 one shot test -- - 6 pll off, ad bypass rd qual 8-bit input to hpf 7 pll off, ad bypass rd comp 8-bit input to hpf 8 pll on, ad bypass srd rrc 8-bit input to hpf 9 pll on, lpf output srd rrc lpf output after scaling 10 pll on, fir output srd rrc fir output after scaling and interpolator 11 pll on, pll phase output srd rrc pll phase error output 12 pll on, pll frequency output srd rrc pll frequency output 13 pll on, peak-to-peak level output srd rrc bits 7 to 1: level_abs; bit 0:wdout 14 pll on, ?ltered level output srd rrc bits 7 to 1: level_fil; bit 0:wdout 15 pll on, differentiator output srd rrc differentiator output after scaling d7 d6 d5 d4 d3 d2 d1 d0 pf.7 pf.6 pf.5 pf.4 pf.3 pf.2 pf.1 pf.0 d7 d6 d5 d4 d3 d2 d1 d0 ----- pf.10 pf.9 pf.8 f s pf 2048 ------------ -
1998 feb 16 20 philips semiconductors product speci?cation qic digital equalizer SZA1000 address 42: phase comparator window shift win_shift is an 8-bit number in twos complement format. the programmed phase shift is 180 win_shift degrees. address 43: pll settings table 37 address 43: pll_ni; note 1 note 1. if ltd (pin 19) is high, ni2 is selected, else ni1. table 38 dl setting; note 1 note 1. the differentiator delay (dl) settings (see table 25) determine the values of q1 and q0 that should be entered. d7 d6 d5 d4 d3 d2 d1 d0 q1 q0 rng.1 rng.0 ni2.1 ni2.0 ni1.1 ni1.0 dl setting q1 q0 dl1 = dl2 1 1 dl1 < dl2 1 0 dl1 > dl2 0 1 table 39 integrating gain factor ki ni ki 0 1 64 1 1 128 2 1 256 3 1 512 table 40 pll range rng pll range 0 64 1 128 2 256 3 512 address 44: pll loop ?lter proportional gain table 41 pll_np; note 1 note 1. if ltd (pin 19) is high, np2 is selected, else np1. d7 d6 d5 d4 d3 d2 d1 d0 -- np2.2 np2.1 np2.0 np1.2 np1. 1 np1. 0
1998 feb 16 21 philips semiconductors product speci?cation qic digital equalizer SZA1000 table 42 proportional gain factor kp m aximum likelihood detector functions address 45: settings table 43 address 45: mld_set notes 1. check for k constraint: k is the maximum number of channel bit-cells allowed without a transition. for mfm code: k = 3 (ks = 4), for rll(1,7) code: k = 7 (ks = 8). 2. check for d = 1 constraint: d is the minimum number of channel bit-cells without transitions that must come between two bit cells with transitions. d = 1 for both mfm and rll(1,7) codes 3. check partial response constraints; delete incorrect peaks. 4. check partial response constraints; add missing peaks. 5. ks=k+1. s tatus register the status register contains 5 status bytes. the contents of the status bytes can be read via the serial interface. table 44 status bytes; notes 1 to 4 notes 1. the levels are measured behind the re-sampling block (interpolator) (see fig.1). 2. actual pll frequency is an 8-bit unsigned number: 3. level_fil can be used for reading of the burst levels, or in an agc loop (with the tza1000 preamplifier). 4. level_pos, level_neg, level_abs and level_fil are 8-bit numbers in twos complement format. np kp 01 1 1 2 2 1 4 3 1 8 4 1 16 5 1 32 6 - 7 - d7 d6 d5 d4 d3 d2 d1 d0 en_k (1) en_d (2) pr1 (3) pr0 (4) ks3 (5) ks2 (5) ks1 (5) ks0 (5) address data name description 255 0 freq actual frequency of pll 255 1 level_pos positive peaks in measured level 255 2 level_neg negative peaks in measured level 255 3 level_abs measured peak-to-peak level 255 4 level_fil low-pass filtered level_abs f s freq 256 ----------------- -
1998 feb 16 22 philips semiconductors product speci?cation qic digital equalizer SZA1000 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistance. 2. equivalent to discharging a 200 pf capacitor through a 25 w series resistance and a 2.5 m h series inductance. thermal characteristics quality specification in accordance with snw-fq-611-e . symbol parameter conditions min. max. unit v ddd1 digital supply voltage - 0.3 +5.5 v v ddd2 digital supply voltage - 0.3 +5.5 v v dda1 analog supply voltage - 0.3 +5.5 v v dda2 analog supply voltage - 0.3 +5.5 v v i input voltage - 0.3 v dd + 0.3 v i i input current on supply pins - 50 +50 ma i i(n) input current on remaining pins - 10 +10 ma p tot maximum total power dissipation - +1100 mw t amb ambient temperature - 30 +85 c t j junction temperature - 30 +125 c t stg storage temperature - 50 +150 c v es(hb) electrostatic handling: human body model note 1 - 3000 +3000 v v es(mm) electrostatic handling: machine model note 2 - 300 +300 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 70 k/w
1998 feb 16 23 philips semiconductors product speci?cation qic digital equalizer SZA1000 characteristics v ddd1 =v ddd2 =v dda1 =v dda2 =5v 5%; f s = f clk(clkin) = 24 mhz; v ref =2v 5%; r ref =10k w , unless otherwise speci?ed . symbol parameter conditions min. typ. max. unit v ddd1 digital supply voltage 4.5 5.0 5.5 v v ddd2 digital supply voltage 4.5 5.0 5.5 v v dda1 analog supply voltage 4.5 5.0 5.5 v v dda2 analog supply voltage 4.5 5.0 5.5 v i ddd1 ; i ddd2 digital supply current r = 2, no weq - 32 80 ma i dda1 ; i dda2 analog supply current stby1 = 0; stby2 = 1; see table 30 - 50 65 ma stby 1= 1; stby2 = 0 - 26 35 ma f clk(clkin) read circuit clock frequency - 24 24 mhz f clk(weqclk) weq circuit clock frequency n6 = 0; see table 14; (3080; 3095) -- 36 mhz v il low-level input voltage -- 0.3v dd v v ih high-level input voltage 0.7v dd -- v v ol low-level output voltage i o = - 4ma -- 0.5 v v oh high-level output voltage i o =+4ma v dd - 0.5 -- v c i input capacitance i/o pins high-z; note 1 -- 5pf analog section v ref reference voltage (pin 37) 1.8 2.0 2.2 v i ref reference current (pin 37) 1.0 1.7 2.1 ma v cnv(a/d) a/d conversion range - 1.6 - v v cm(a/d) a/d common mode voltage 2 2.5 3 v r i(a/d) a/d input resistance 2.3 3.3 4.4 k w c i(a/d) a/d input capacitance - 35 pf i i(32) dc input current (ina) - 0.42 0.6 ma i i(33) dc input current (inb) - 0.13 0.2 ma v 38 voltage on pin 38 (r ref ) - 2.0 - v i o(1) output current on pin 1 (io1) idac1 = 0; see table 20 - 0.0 0.05 ma idac1 = 31 1.40 1.95 2.60 ma i o(2) output current on pin 2 (io2) idac2 = 0; see table 20 - 0.0 0.05 ma idac2 = 31 1.40 1.95 2.60 ma v o(dif) d/a differential output range (peak-to-peak) note 2 1.5 1.72 1.8 v v cm(d/a) d/a common mode voltage note 2 1.0 1.16 1.4 v
1998 feb 16 24 philips semiconductors product speci?cation qic digital equalizer SZA1000 f - 3db(cutoff)(lpf) - 3db cut-off frequency, analog lpf (dac ?lter) note 2 - 8 - mhz v cm(comp) comparator common mode voltage note 3 1.0 1.16 1.4 v r i(comp) comparator input resistance note 4 17 26 35 k w v io(comp) comparator offset voltage note 4 -- 45 mv serial interface f clk(sio) serial i/f clock -- 1 4 f s mhz t su(d-clk) set-up time: data-to-clock 10 -- ns t h(d-clk) hold time: data-to-clock note 5 t s +10 -- ns t d(1) delay clock: new data -- 2t s +10 ns t d(2) delay clock: old data t s -- ns t su(en-clk) set-up time: enable-to-clock t s +10 -- ns t h(en-clk) hold time: enable-to-clock t s +10 -- ns digital read section t clkinh clkin high time 15 -- ns t clkinl clkin low time 15 -- ns t rdl rd low time t s - 2t s +10 ns t su(srd-rrc) set-up time: srd-to-rrc note 6 t clkinl - 5 - 0.2c o(l)(srd) - t clkinl +2 - 0.2c o(l)(rrc) ns t h(srd-rrc) hold time: srd-to-rrc note 6 t clkinh - 2 - 0.2c o(l)(rrc) -- ns t rrcl rrc low time note 6 t clkinl - 5 - 0.2c o(l)(rrc) - t clkinl ns t su(aux-clkin) input set-up time: auxbus-to-clkin (pin 6) --- ns t h(aux-clkin) input hold time: auxbus-to-clkin (pin 6) --- ns t paclkh paclk high time note 7 t clkinh - 2 - 0.2c o(l)(paclk) - t clkinh ns t paclkl paclk low time note 7 t clkinl - 5 - 0.2c o(l)(paclk) - t clkinl ns t d(aux-paclk) delay: auxbus-to-paclk (pin 29) note 8 -- 10 + 0.2c o(l)(aux) ns t d(paclk-aux) delay: paclk to auxbus notes 7 and 8 -- 5+ 0.2c o(l)(paclk) ns symbol parameter conditions min. typ. max. unit
1998 feb 16 25 philips semiconductors product speci?cation qic digital equalizer SZA1000 notes 1. pins 3, 4, 6, 9 to 20, 22, 23, 24, 30 and 31. 2. measured at pins 39 and 44 with a 10 m w /15 pf load. 3. measured at pins 40 and 43. 4. differential pins 40 and 43. 5. 6. c o(l)(srd) is the external load (pf), at srd (pin 27) for c o(l)(srd) < 50 pf. c o(l)(rrc) is the external load (pf), at rrc (pin 25) for c o(l)(rrc) < 50 pf. 7. c o(l)(paclk) is the external load (pf), at paclk (pin 29) for c o(l)(paclk) < 50 pf. 8. c o(l)(aux) is the external load (pf), at aux0 to aux7 (pins 11 to 18) for c o(l)(aux) < 50 pf. 9. c o(l)(wdout) is the external load (pf), at wdout (pin 11) for c o(l)(wdout) < 50 pf. write equalization section f clk(weq) weq clock frequency n2 = 1 or n3 = 1; see table 14 -- 36 mhz n6 =1; see table 14 - 24 24 mhz t weql weq low time 10 -- ns t weqh weq high time 10 -- ns t su(wd-weqclk) setup time: wdin-to-weqclk n2=1 or n3=1; see table 14 5 -- ns t h(wd-weqclk) hold time: wd-to-weqclk n2 = 1 or n3 = 1; see table 14 10 -- ns t il(wdin) wdin input low time (wdi mode) wdi_i = 0; see table 15 10 -- ns t ol(wdout) wdout output low time (wdi mode) note 9 t weqh - 2 - 0.2 c o(l)(wdout) - t weqh ns d f o(wdin-weqclk) frequency offset wdin-weqclk n6=1; see table 14 0.5 -- % symbol parameter conditions min. typ. max. unit t s 1 f s --- - =
1998 feb 16 26 philips semiconductors product speci?cation qic digital equalizer SZA1000 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... timing diagrams serial interface u ll pagewidth mgg656 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 3-state write settings sden sclk sdio a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 3-state read status sden sclk sdio address and data from microcontroller data out from device t h(en-clk) t su(d-clk) t h(d-clk) t su(en-clk) t h(en-clk) t su(en-clk) t h(en-clk) t su(d-clk) t h(d-clk) t su(en-clk) t h(en-clk) t su(en-clk) t d(1) t d(2) fig.8 serial i/o showing set-up, hold and delay timing.
1998 feb 16 27 philips semiconductors product speci?cation qic digital equalizer SZA1000 digital read section write equalization section fig.9 digital read section showing set-up, hold and delay timing. handbook, full pagewidth mgg657 t paclkl t paclkh t d(aux-paclk) t d(paclk-aux) t clkinl t clkinh t su(srd-rrc) t h(srd-rrc) t h(aux-clkin) t su(aux-clkin) srd rrc clkin aux0 to 7 input paclk aux0 to 7 output fig.10 weq section showing set-up and hold timing. handbook, full pagewidth mgg658 t h(wd-weqclk) weqclk) wdin (wdi mode) wdin (wd mode) wdout (wdi mode) t weqh t weql t su(wd-weqclk) t ol(wdout) t il(wdin)
1998 feb 16 28 philips semiconductors product speci?cation qic digital equalizer SZA1000 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1998 feb 16 29 philips semiconductors product speci?cation qic digital equalizer SZA1000 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all qfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 feb 16 30 philips semiconductors product speci?cation qic digital equalizer SZA1000 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1998 feb 16 31 philips semiconductors product speci?cation qic digital equalizer SZA1000 notes
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